David G. Seiler

National Institute of Standards and Technology (NIST)

Biography:

Dr. David Seiler is Chief of the Semiconductor and Dimensional Metrology Division at the National Institute of Standards and Technology (NIST), working with industry to provide innovative research and standards for dimensional, nanometer-scale, surface, and acoustic pressure measurements; semiconductors; MEMS; power electronics; nanoelectronics; smart grid; and flexible/printed electronics. He has worked for almost two decades on the International Technology Roadmap for Semiconductors, recognized worldwide as a model for evaluating industry challenges and technology requirements and then formulating potential solutions. He has made substantial contributions to government-industry collaborations such as the Nanoelectronics Research Initiative and SEMATECH. He also works with industry by serving on the Governing Counsel of the Nanoelectronics Research Initiative and as the Chair of AIP’s Corporate Associates. In 1995, Dr. Seiler initiated the International Conference on Frontiers of Characterization and Metrology for Nanoelectronics, which he continues to lead today. The conference summarizes major issues for next generation semiconductor manufacturing and its talks are widely disseminated (over 3.5 M page views since 2000).

He has expertise in properties of semiconductors with focus on quantum transport, two-photon absorption spectroscopy, and magneto-optical effects. He has chaired and been editor of 11 international semiconductor conferences. Before joining NIST in 1988, Dr. Seiler served as a Solid State Physics Program Director in the NSF Materials Research Division, spent a sabbatical at the MIT Francis Bitter National Magnet Laboratory, and was Regents Professor of Physics at the University of North Texas. Dr. Seiler received a Ph. D. and M.S. in Physics from Purdue University and a B.S. in Physics from Case Western Reserve University. He is Fellow of the APS and the IEEE. He also received a Purdue Distinguished Alumnus Award for Semiconductor Physics Leadership.